S71PL129JC0 Datasheet, PDF (139/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance information
Timing Diagrams
Read Timings
tRC
ADDRESS
tASC
ADDRESS VALID
tCE
tCHAH
tASC
CE1#
tCP
tOE
tCHZ
OE#
LB#/ UB#
DQ
(Output)
tBLZ
tOLZ
tCLZ
tOHZ
tBA
tBHZ
VALID DATA OUTPUT _tOH
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 55. Read Timing #1 (Basic Timing)
ADDRESS
CE1# _Low
OE#
tRC
ADDRESS VALID
tAA
tASO
tOE
tAx
tRC
ADDRESS VALID
tAA
tOHAH
LB#/UB#
DQ
(Output)
tOLZ
tOH
tOHZ
tOH
VALID DATA OUTPUT
Note: This timing diagram assumes CE2=H and WE#=H.
VALID DATA OUTPUT
Figure 56. Read Timing #2 (OE# Address Access
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
139