S71PL129JC0 Datasheet, PDF (56/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 =
0 in cycle 6, program command must be issued and verified again.
7. Data is latched on the rising edge of WE#.
8. Entire command sequence must be entered for each portion of password.
9. Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at addresses 0-3.
11. A 2 µs timeout is required between any two portions of password.
12. A 100 µs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase
command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB
overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
Write Operation Status
The device provides several bits to determine the status of a program or erase opera-
tion: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 14 and the following subsections describe
the function of these bits. DQ7 and DQ6 each offer a method for determining whether
a program or erase operation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine whether an Embedded Program
or Erase operation is in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Pro-
gram or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-
mand sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement
of the datum programmed to DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is complete, the device out-
puts the datum programmed to DQ7. The system must provide the program address
to read valid status information on DQ7. If a program address falls within a protected
sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns
to the read mode.
56
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004