S71PL129JC0 Datasheet, PDF (64/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
DC Characteristics
Table 15. CMOS Compatible
Parameter
Symbol
Parameter Description
I_LI
Input Load Current
I_LIT
A9, OE#, RESET# Input Load Current
I_LR
Reset Leakage Current
I_LO
Output Leakage Current
I_CC1
I_CC2
I_CC3
I_CC4
I_CC5
I_CC6
I_CC7
I_CC8
I_CC9
V_IL
V_IH
V_HH
V_ID
V_OL
V_OH
V_LKO
V_CC Active Read Current (Notes 1, 2)
V_CC Active Write Current (Notes 2, 3)
V_CC Standby Current (Note 2)
V_CC Reset Current (Note 2)
Automatic Sleep Mode (Notes 2, 4)
V_CC Active Read-While-Program Current
(Notes 1, 2)
V_CC Active Read-While-Erase Current
(Notes 1, 2)
V_CC Active Program-While-Erase-
Suspended Current (Notes 2, 5)
V_CC Active Page Read Current (Note 2)
Input Low Voltage
Input High Voltage
Voltage for ACC Program Acceleration
Voltage for Autoselect and Temporary
Sector Unprotect
Output Low Voltage
Output High Voltage
Low V_CC Lock-Out Voltage (Note 5)
Test Conditions
V_IN = V_SS to V_CC,
V_CC = V_{CC max}
V_CC = V_{CC max}; V_ID= 12.5 V
V_CC = V_{CC max}; V_ID= 12.5 V
V_OUT = V_SS to V_CC, OE# = V_IH
V_CC = V_{CC max}
OE# = V_IH, V_CC = V_{CC max}
(Note 1)
5 MHz
10 MHz
OE# = V_IH, WE# = V_IL
CE#, RESET#, WP#/ACC
= V_IO ± 0.3 V
RESET# = V_SS ± 0.3 V
V_IH = V_IO ± 0.3 V;
V_IL = V_SS ± 0.3 V
OE# = V_IH,
5 MHz
10 MHz
OE# = V_IH,
5 MHz
10 MHz
OE# = V_IH
OE# = V_IH, 8 word Page Read
V_IO = 2.7–3.6 V
V_IO = 2.7–3.6 V
V_CC = 3.0 V ± 10%
V_CC = 3.0 V ± 10%
I_OL = 2.0 mA, V_CC = V_{CC min}, V_IO = 2.7–3.6
V
I_OH = –2.0 mA, V_CC = V_{CC min}, V_IO = 2.7–3.6
V
Min
–0.5
2.0
8.5
11.5
2.4
2.3
Typ
Max
Unit
±1.0
µA
35
µA
35
µA
±1.0
µA
20
30
mA
45
55
15
25
mA
0.2
5
µA
0.2
5
µA
0.2
5
µA
21
45
mA
46
70
21
45
mA
46
70
17
25
mA
10
15
mA
0.8
V
V_CC+0.3
V
9.5
V
12.5
V
0.4
V
V
2.5
V
Notes:
1. The I_CC current listed is typically less than 5 mA/MHz, with OE# at V_IH.
2. Maximum I_CC specifications are tested with V_CC = V_CCmax.
3. I_CC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC + 30 ns. Typical sleep
mode current is 1 mA.
5. Not 100% tested.
6. In S29PL129J there are two CE# (CE1#, CE2#).
7. Valid CE1#/CE2# conditions: (CE1# = V_IL, CE2# = V_IH,) or (CE1# = V_IH, CE2# = V_IL) or (CE1# = V_IH, CE2# = V_IH)
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S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004