S71PL129JC0 Datasheet, PDF (142/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
ADDRESS
CE1#
WE#
tOHAH
Low
tAS
tWC
ADDRESS VALID
tWP
tWR
tAS
tWHP
tWC
ADDRESS VALID
tWP
tWR
LB#, UB#
tOES
OE#
tOHZ
DQ
(Input)
tDS
tDH
VALID DATA INPUT
Note:This timing diagram assumes CE2=H.
tDS
tDH
VALID DATA INPUT
Figure 61. Write Timing #2 (WE# Control)
tWC
tWC
ADDRESS
ADDRESS VALID
ADDRESS VALID
CE1# _Low
tAS
WE#
LB#
tBS
UB#
DQ1-8
(Input)
DQ9-16
(Input)
tWP
tAS
tWHP
tWR
tBS
tBH
tDS
tDH
VALID DATA INPUT
tWP
tBH
tWR
tDS
tDH
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 62. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control)
142
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004