S71PL129JC0 Datasheet, PDF (144/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Read/Write Timings
ADDRESS
CE1#
WE#
tCHAH
tAS
tCP
tWC
WRITE ADDRESS
tCW
tWR
tASC
tCP
tRC
READ ADDRESS
tCE
tCHAH
UB#, LB#
tOHCL
OE#
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
Notes:
1. This timing diagram assumes CE2=H.
2. Write address is valid from either CE1# or WE# of last falling edge.
Figure 65. Read/Write Timing #1-1 (CE1# Control)
ADDRESS
CE1#
WE#
tCHAH
tAS
tCP
tWC
WRITE ADDRESS
tWR
tASC
tCP
tWP
tRC
READ ADDRESS
tCE
tCHAH
UB#, LB#
OE#
DQ
tOHCL
tCHZ
tOH
tDS
tDH
tOE
tOLZ
tOH
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Notes:
1. This timing diagram assumes CE2=H.
2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
Figure 66. Read / Write Timing #1-2 (CE1#/WE#/OE# Control)
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pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004