S71PL129JC0 Datasheet, PDF (127/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Address¹⁾
A1~A0
CS1#
Valid
Address
Valid
Address
tAA
Valid
Valid
Valid
Address Address Address
tPC
CS2
tCO
OE#
DQ15~DQ0
High Z
tPA
tOE
tOHZ
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Figure 48. Timing Waveform of Page Cycle (Page Mode Only)
Notes:
1. 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21, 128Mb: A2 ~ A22.
t_HZ and t_OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
At any given temperature and voltage condition, t_HZ(Max.) is less than t_LZ(Min.) both for a given device and from device
to device interconnection.
t_OE(max) is met only when OE# becomes enabled after t_AA(max).
If invalid address signals shorter than min. t_RC are continuously repeated for over 4µs, the device needs a normal read
timing (t_RC) or needs to sustain standby state for min. t_RC at least once in every 4µs.
Write Timings
Address
CS1#
tWC
tCW
tWR
CS2
UB#, LB#
WE#
Data in
Data out
tAW
tBW
tWP
tAS
tDW
tDH
High-Z
Data Valid
tWHZ
tOW
Data Undefined
Figure 49. Write Cycle #1 (WE# Controlled)
High-Z
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
127