S71PL129JC0 Datasheet, PDF (43/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Addresses
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
Data
0027h
0036h
0000h
0000h
0003h
0000h
0009h
0000h
0004h
0000h
0004h
0000h
Table 9. System Interface String
Description
V_CC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
V_CC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
V_PP Min. voltage (00h = no V_PP pin present)
V_PP Max. voltage (00h = no V_PP pin present)
Typical timeout per single byte/word write 2^N µs
Typical timeout for Min. size buffer write 2^N µs (00h = not supported)
Typical timeout per individual block erase 2^N ms
Typical timeout for full chip erase 2^N ms (00h = not supported)
Max. timeout for byte/word write 2^N times typical
Max. timeout for buffer write 2^N times typical
Max. timeout per individual block erase 2^N times typical
Max. timeout for full chip erase 2^N times typical (00h = not supported)
Addresses
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
Table 10. Device Geometry Definition
Data
0018h (PL129J)
0001h
0000h
0000h
0000h
0003h
0007h
0000h
0020h
0000h
00FDh (PL129J)
0000h
0000h
0001h
0007h
0000h
0020h
0000h
0000h
0000h
0000h
0000h
Device Size = 2^N byte
Description
Flash Device Interface description (refer to CFI publication 100)
Max. number of byte in multi-byte write = 2^N
(00h = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Addresses
40h
41h
42h
Table 11. Primary Vendor-Specific Extended Query
Data
0050h
0052h
0049h
Description
Query-unique ASCII string “PRI”
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
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