S71PL129JC0 Datasheet, PDF (114/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
ZZ#
CE#
t_ZZMIN
t_CDZZ
t_R
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)
A4
t_AS
CE#
WE#
t_WC
t_AW
t_WP
t_WR
LB#, UB#
t_ZZWE
t_BW
t_R
ZZ#
t_ZZMIN
Figure 42. Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M)
Mode Register Update and Deep Sleep Timings
Item
Chip deselect to ZZ# low
ZZ# low to WE# low
Write register cycle time
Chip enable to end of write
Address valid to end of write
Write recovery time
Address setup time
Write pulse width
Deep Sleep Pulse Width
Deep Sleep Recovery
Symbol
t_CDZZ
t_ZZWE
t_WC
t_CW
t_AW
t_WR
t_AS
t_WR
t_ZZMIN
t_R
Min
5
10
70/85
70/85
70/85
0
0
40
10
200
Notes:
1. Minimum cycle time for writing register is equal to speed grade of product.
Max
Unit
ns
500
ns
ns
ns
ns
ns
ns
ns
µs
µs
Note
1
1
1
114
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004