S71PL129JC0 Datasheet, PDF (20/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Random Read (Non-Page Read)
Address access time (t_ACC) is equal to the delay from stable addresses to valid
output data. The chip enable access time (t_CE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE# to valid data at the out-
put inputs (assuming the addresses have been stable for at least t_ACC–t_OE time).
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. Address bits Amax–A3 select an 8 word page,
and address bits A2–A0 select a specific word within that page. This is an asyn-
chronous operation with the microprocessor supplying the specific word location.
The random or initial page access is t_ACC or t_CE and subsequent page read ac-
cesses (as long as the locations specified by the microprocessor falls within that
page) is equivalent to t_PACC. When CE1# and CE#2 are deasserted (=V_IH), the
reassertion of CE1# or CE#2 for subsequent access has access time of t_ACC or
t_CE. Here again, CE1#/CE#2 selects the device and OE# is the output control and
should be used to gate data to the output inputs if the device is selected. Fast
page mode accesses are obtained by keeping Amax–A3 constant and changing
A2–A0 to select the specific word within that page.
Table 2. Page Select
Word
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, and
erase-suspend program), the device is capable of reading data from one bank of
memory while a program or erase operation is in progress in another bank of
memory (simultaneous operation). The bank can be selected by bank addresses
(A21–A19) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
Bank
Bank 1A
Bank 1B
20
CE1#
0
0
CE2#
1
1
S29PL129J for MCP
PL129J: A21–A20
00
01, 10, 11
S29PL129J_MCP_00_A0 June 4, 2004