S71PL129JC0 Datasheet, PDF (123/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
64M pSRAM
Item
Average Operating
Current
Symbol
I_CC1
Async
I_CC2
Page
Standby Current (CMOS)
I_SB1 (Note 1)
Test Conditions
Min Typ Max Unit
Cycle time=1µs, 100% duty, I_IO=0mA,
CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2≥V_CC-0.2V, V_IN≤0.2V or V_IN≥VCC-0.2V
— — TBD mA
Cycle time=Min, I_IO=0mA, 100% duty,
CS1#=V_IL, CS2=V_IH LB#=V_IL and/or UB#=V_IL, — — TBD mA
V_IN=V_IH or V_IL
Cycle time=t_RC+3t_PC, I_IO=0mA, 100% duty,
CS1#=V_IL, CS2=V_IH LB#=V_IL and/or UB#=V_IL,
V_IN-V_IH or V_IL
TBD mA
Other inputs=0-VCC
1. CS1# ≥ V_CC - 0.2, CS2 ≥ V_CC - 0.2V (CS1#
controlled) or
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
— — TBD mA
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
128M pSRAM
Item
Symbol
Test Conditions
Min Typ Max Unit
Average Operating
Current
Cycle time=1µs, 100% duty, I_IO=0mA, CS1#≤0.2V,
I_CC1
LB#≤0.2V and/or UB#≤0.2V, CS2≥V_CC-0.2V, V_IN≤0.2V or
—
V_IN≥VCC-0.2V
I_CC2
Cycle time=t_RC+3t_PC, I_IO=0mA, 100% duty, CS1#=V_IL,
CS2=V_IH LB#=V_IL and/or UB#=V_IL, V_IN-V_IH or V_IL
—
Other inputs=0-V_CC
Standby Current (CMOS) I_SB1 (Note 1) ^{1. CS1# ≥ V}CC ^{- 0.2, CS2 ≥ V}CC ^{- 0.2V (CS1# controlled) or} —
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
— TBD mA
— TBD mA
— TBD mA
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. I_SB1 is measured after 60ms from
the time when standby mode is set up.
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
123