S71PL129JC0 Datasheet, PDF (136/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
AC Characteristics
Write Operation
16M
32M
64M
Parameter
Symbol Min. Max. Min. Max. Min. Max. Unit Notes
Write Cycle Time
t_WC
70 1000 65 1000 65 1000 ns
1,2
Address Setup Time
t_AS
0
—
0
—
0
—
ns
3
CE1# Write Pulse Width
t_CW
45
—
40
—
40
—
ns
3
WE# Write Pulse Width
t_WP
45
—
40
—
40
—
ns
3
LB#/UB# Write Pulse Width
t_BW
45
—
40
—
40
—
ns
3
LB#/UB# Byte Mask Setup Time
t_BS
-5
—
–5
—
–5
—
ns
4
LB#/UB# Byte Mask Hold Time
t_BH
-5
—
–5
—
–5
—
ns
5
Write Recovery Time
t_WR
0
—
0
—
0
—
ns
6
CE1# High Pulse Width
t_CP
10
—
12
—
12
—
ns
WE# High Pulse Width
t_WHP 7.5 1000 7.5 1000 7.5 1000 ns
7
LB#/UB# High Pulse Width
t_BHP
10 1000 12 1000 12 1000 ns
Data Setup Time
t_DS
15
—
12
—
12
—
ns
Data Hold Time
t_DH
0
—
0
—
0
—
ns
OE# High to CE1# Low Setup Time for Write t_OHCL
-5
—
–5
—
–5
—
ns
8
OE# High to Address Setup Time for Write
t_OES
0
—
0
—
0
—
ns
9
LB# and UB# Write Pulse Overlap
t_BWO
30
—
30
—
30
—
ns
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system
operation, please contact local Spansion representative for the relaxation of 1µs limitation.
2. Minimum value must be equal or greater than the sum of write pulse (t_CW, t_WP or t_BW) and write recovery time (t_WR).
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
occurs last.
5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
occurs first.
6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7. t_WPH minimum is absolute minimum value for device to detect High level. And it is defined at minimum V_IH level.
8. If OE# is Low after minimum t_OHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum t_RC is met.
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum t_RC is met and data
bus is in High-Z.
136
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004