S71PL129JC0 Datasheet, PDF (146/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
CE1#
CE2
tC2LH
tCHS
tCHH
VDD
VDD min
0V
Note: The t_C2LH specifies after V_DD reaches specified minimum level.
Figure 69. Power-up Timing #1
CE1#
tCHH
CE2
VDD
0V
VDD min
Note: The t_CHH specifies after V_DD reaches specified minimum level and applicable to both CE1# and CE2.
Figure 70. Power-up Timing #2
CE1#
CE2
DQ
tCSP
Power Down Entry
tCHS
tC2LP
High-Z
Power Down Mode
tCHH (tCHHP)
Power Down Exit
Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and
Power-Down program was not performed prior to this reset.
Figure 71. Power Down Entry and Exit Timing
146
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004