S71PL129JC0 Datasheet, PDF (69/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Erase/Program Operations
Table 20. Erase and Program Operations
Parameter
JEDEC
Std Description
t_AVAV
t_AVWL
t_WC Write Cycle Time (Note 1)
t_AS Address Setup Time
t_ASO
Address Setup Time to OE# low during toggle bit
polling
t_WLAX
t_AH Address Hold Time
t_AHT
Address Hold Time From CE1#, CE#2 or OE# high
during toggle bit polling
t_DVWH
t_WHDX
t_GHWL
t_DS
t_DH
t_OEPH
t_GHWL
Data Setup Time
Data Hold Time
Output Enable High during toggle bit polling
Read Recovery Time Before Write
(OE# High to WE# Low)
t_ELWL
t_WHEH
t_WLWH
t_WHDL
t_WHWH1
t_WHWH1
t_WHWH2
t_CS CE1# or CE#2 Setup Time
t_CH CE1# or CE#2 Hold Time
t_WP Write Pulse Width
t_WPH Write Pulse Width High
t_SR/W Latency Between Read and Write Operations
t_WHWH1 Programming Operation (Note 4)
t_WHWH1 Accelerated Programming Operation (Note 4)
t_WHWH2 Sector Erase Operation (Note 4)
t_VCS V_CC Setup Time (Note 1)
t_RB Write Recovery Time from RY/BY#
t_BUSY Program/Erase Valid to RY/BY# Delay
Speed Options
55
60
65
70 Unit
Min 55 60 65 70 ns
Min
0
ns
Min
15
ns
Min 30
35
ns
Min
0
ns
Min 25
30
ns
Min
0
ns
Min
10
ns
Min
0
ns
Min
0
ns
Min
0
ns
Min
35
ns
Min 20
25
ns
Min
0
ns
Typ
6
µs
Typ
4
µs
Typ
0.5
sec
Min
50
µs
Min
0
ns
Max
90
ns
Min
35
ns
Notes:
1. Not 100% tested.
2. S29PL129J - During CE1# transitions, CE2# = V_IH; During CE2# transitions, CE1# = V_IH
3. S29PL129J - There are two CE# (CE1#, CE2#).
4. See Table 25, “Erase And Programming Performance,” on page 78 for more information.
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
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