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| S71PL129JC0 Datasheet, PDF (147/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory | |||
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Advance information
CE1#
OE#
tCHOX
tCHWX
WE#
Active (Read)
Standby
Active (Write)
Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes
tRC (min) period for Standby mode from CE1# Low to High transition.
Figure 72. Standby Entry Timing after Read or Write
ADDRESS
CE1#
tRC
MSB*1
tWC
MSB*1
tWC
MSB*1
tWC
MSB*1
tWC
MSB*1
tRC
Key*2
tCP
tCP
tCP
tCP
tCP
tCP*3
OE#
WE#
LB#, UB#
DQ*3
RDa
RDa
RDa
X
X
RDb
Cycle #1
Cycle #2
Cycle #3
Cycle #4
Cycle #5
Cycle #6
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2. The address key must confirm the format specified in page 132. If not, the operation and data are not guaranteed.
3. After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
Figure 73. Power Down Program Timing (for 32M/64M Only)
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
147
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