S71PL129JC0 Datasheet, PDF (78/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
CE1#
CE2#
t_CCR
t_CCR
Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control
Parameter
Sector Erase Time
Chip Erase Time
Table 25. Erase And Programming Performance
PL129J
Typ (Note 1)
0.5
135
Max (Note 2)
Unit
2
sec
216
sec
Word Program Time
6
100
µs
Accelerated Word Program Time
Chip Program Time
(Note 3)
PL129J
4
50.4
60
µs
200
sec
Comments
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90°C, V_CC = 2.7 V, 1,000,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 12 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
BGA Pin Capacitance
Parameter Symbol
C_IN
C_OUT
C_IN2
C_IN3
Parameter Description
Input Capacitance
Output Capacitance
Control Pin Capacitance
WP#/ACC Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions T_A = 25°C, f = 1.0 MHz.
Test Setup
V_IN = 0
V_OUT = 0
V_IN = 0
V_IN = 0
Typ Max Unit
6.3
7
pF
7.0
8
pF
5.5
8
pF
11
12
pF
78
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004