S71PL129JC0 Datasheet, PDF (131/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance information
Functional Description
Mode
Standby (Deselect)
Output Disable (Note 1)
Output Disable (No Read)
Read (Upper Byte)
Read (Lower Byte)
Read (Word)
No Write
Write (Upper Byte)
Write (Lower Byte)
Write (Word)
Power Down
CE2#
H
CE1#
H
WE#
X
H
OE#
X
H
H
L
H
L
L
H
L
X
X
X
LB#
X
X
H
H
L
L
H
H
L
L
X
UB#
X
X
H
L
H
L
H
L
H
L
X
A_21-0
X
Note 3
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
X
DQ_8-1
High-Z
High-Z
High-Z
High-Z
Output Valid
Output Valid
Invalid
Invalid
Input Valid
Input Valid
High-Z
DQ_16-9
High-Z
High-Z
High-Z
Output Valid
High-Z
Output Valid
Invalid
Input Valid
Invalid
Input Valid
High-Z
Legend:L = V_IL, H = V_IH, X can be either V_IL or V_IH, High-Z = High Impedance.
Notes:
1. Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of
1ms limitation.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of the Power-Down Program, 16M has data retention in all modes except Power Down. Refer to Power Down for
details.
3. Can be either V_IL or V_IH but must be valid before Read or Write.
Power Down (for 32M, 64M Only)
Power Down
The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the
device in power-down mode and maintains the low-power idle state as long as
CE2 is kept Low. CE2 High resumes the device from power-down mode. These
devices have three power-down modes. These can be programmed by series of
read/write operation. Each mode has following features.
Mode
Sleep (default)
4M Partial
8M Partial
32M
Retention Data
No
4M bit
8M bit
Retention Address
N/A
00000h to 3FFFFh
00000h to 7FFFFh
Mode
Sleep (default)
8M Partial
16M Partial
64M
Retention Data
No
8M bit
16M bit
Retention Address
N/A
00000h to 7FFFFh
00000h to FFFFFh
The default state is Sleep and it is the lowest power consumption but all data is
lost once CE2 is brought to Low for Power Down. It is not required to program to
Sleep mode after power-up.
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
131