S71PL129JC0 Datasheet, PDF (126/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Timing Diagrams
Read Timings
Address
Data Out
tRC
tAA
tOH
Previous Data Valid
Data Valid
Figure 46. Timing Waveform of Read Cycle(1)
Notes:
1. Address Controlled, CS1#=OE#=V_IL, CS2=WE#=V_IH, UB# and/or LB#=V_IL.
Address
CS1#
tRC
tAA
tOH
tCO
CS2
UB#, LB#
OE#
Data out
Notes:
1. WE#=V_IH.
tBA
tOE
High-Z
tOLZ
tBLZ
tLZ
Data Valid
Figure 47. Timing Waveform of Read Cycle(2)
tHZ
tBHZ
tOHZ
126
Type 2 pSRAM
pSRAM_Type02_15A1 June 25, 2004