S71PL129JC0 Datasheet, PDF (145/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance information
ADDRESS
CE1#
tOHAH
Low
WE#
tOES
tWC
WRITE ADDRESS
tAS
tWP
tWR
tRC
READ ADDRESS
tAA
tOHAH
UB#, LB#
OE#
DQ
tOHZ
tOH
tASO
tOE
tWHOL
tDS
tDH
tOLZ
tOHZ
tOH
READ DATA OUTPUT
WRITE DATA INPUT
Notes:
1. This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
READ DATA OUTPUT
Figure 67. Read / Write Timing #2 (OE#, WE# Control)
ADDRESS
CE1#
Low
tOHAH
tWC
WRITE ADDRESS
tRC
READ ADDRESS
tAA
tOHAH
WE#
UB#, LB#
OE#
DQ
tOES
tAS
tBHZ
tOH
tBW
tDS
tWR
tBA
tASO
tWHOL
tDH
tBLZ
tBHZ
tOH
READ DATA OUTPUT
WRITE DATA INPUT
Notes:
1. This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
READ DATA OUTPUT
Figure 68. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
145