S71PL129JC0 Datasheet, PDF (66/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
VIO
0.0 V
In
VIO/2
Measurement Level
VIO/2
Figure 10. Input Waveforms and Measurement Levels
Output
VCC RampRate
All DC characteristics are specified for a V_CC ramp rate > 1V/100 µs and V_CC
>=V_CCQ - 100 mV. If the V_CC ramp rate is < 1V/100 µs, a hardware reset
required.+
Read Operations
Table 18. Read-Only Operations
Parameter
JEDEC Std. Description
Test Setup
t_AVAV
t_AVQV
t_ELQV
t_GLQV
t_EHQZ
t_GHQZ
t_RC Read Cycle Time (Note 1)
t_ACC Address to Output Delay
t_CE Chip Enable to Output Delay
t_PACC Page Access Time
t_OE Output Enable to Output Delay
t_DF Chip Enable to Output High Z (Note 3)
t_DF
Output Enable to Output High Z
(Notes 1, 3)
Min
CE#, OE# = V_IL Max
OE# = V_IL
Max
Max
Max
Max
Max
t_AXQX
t_OH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 3)
Min
Read
Min
t_OEH
Output Enable Hold
Time (Note 1)
Toggle and
Data# Polling
Min
Speed Options
55 60 65 70 Unit
55 60 65 70 ns
55 60 65 70 ns
55 60 65 70 ns
20 25 25 30 ns
20 25
30
ns
16
ns
16
ns
5
ns
0
ns
10
ns
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 16 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V_CC /2. The time from OE#
high to the data bus driven to V_CC /2 is taken as t_DF.
4. S29PL129J has two CE# (CE1#, CE2#).
5. Valid CE1# / CE2# conditions: (CE1# = V_IL,CE2# = V_IH) or (CE1# = V_IH,CE2# = V_IL) or (CE1# = V_IH, CE2# = V_IH)
6. Valid CE1# / CE2# transitions: (CE1# = V_IL,CE2# = V_IH) or (CE1# = V_IH,CE2# = V_IL) to (CE1# = CE2# = V_IH)
7. Valid CE1# / CE2# transitions: (CE1# = CE2# = V_IH) to (CE1# = V_IL,CE2# = V_IH) or (CE1# = V_IH,CE2# = V_IL)
8. For 70pF Output Load Capacitance, 2 ns is added to the above t_ACC,t_CE,t_PACC,t_OE values for all speed grades
66
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004