S71PL129JC0 Datasheet, PDF (129/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Address
CS1#
CS2
UB#, LB#
WE#
Data in
tWC
tCW
tWR
tAW
tBW
tAS
tWP
tDW
tDH
Data Valid
Data out
High-Z
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)
Notes:
1. A write occurs during the overlap (t_WP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low
with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A
write ends at the earliest transition when CS1# goes high and WE# goes high. The t_WP is measured from the beginning of
write to the end of write.
2. t_CW is measured from the CS1# going low to the end of write.
3. t_AS is measured from the address valid to the beginning of write.
4. t_WR is measured from the end of write to the address change. t_WR is applied in case a write ends with CS1# or WE# going
high.
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
129