S71PL129JC0 Datasheet, PDF (140/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
tAX
tRC
ADDRESS
tAA
ADDRESS VALID
CE1#, OE# Low
tBA
tBA
LB#
UB#
DQ1-8
(Output)
DQ9-16
(Output)
tBHZ
tBLZ
tOH
VALID DATA
OUTPUT
tBA
tBLZ
tBLZ
VALID DATA
OUTPUT
Note: This timing diagram assumes CE2=H and WE#=H.
VALID DATA OUTPUT
Figure 57. Read Timing #3 (LB#/UB# Byte Access)
tAx
tBHZ
tOH
tBHZ
tOH
ADDRESS
(A21-A3)
ADDRESS
(A2-A0)
CE1#
OE#
tRC
ADDRESS VALID
tASC
tCE
tRC
ADDRESS VALID
tPRC
ADDRESS
VALID
tPAA
tPRC
ADDRESS
VALID
tPAA
tPRC
ADDRESS
VALID
tPAA
tCHAH
tCHZ
LB#/UB#
tCLZ
tOH
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Normal Access)
VALID DATA OUTPUT
(Page Access)
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 58. Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only)
140
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004