S71PL129JC0 Datasheet, PDF (19/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels re-
quired, and the resulting output. The following subsections describe each of these
operations in further detail.
Read
Operation
Write
Standby
Output Disable
Reset
Temporary Sector Unprotect
(High Voltage)
Table 1. PL129J Device Bus Operations
CE1# CE2# OE# WE# RESET# WP#/ACC
L
H
L
H
H
X
H
L
L
H
H
L
H
L
H
X
(Note 2)
V_IO±
0.3 V
V_IO ±
0.3 V
X
X
V_IO ±
0.3 V
X
L
L
H
H
H
X
X
X
X
X
L
X
X
X
X
X
V_ID
X
Addresses
(A21–A0)
A_IN
A_IN
X
X
X
A_IN
DQ15–
DQ0
D_OUT
D_IN
High-Z
High-Z
High-Z
D_IN
Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID = 11.5–12.5 V, V_HH = 8.5–9.5 V, X = Don’t Care, SA = Sector
Address, A_IN = Address In, D_IN = Data In, D_OUT = Data Out
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
““High Voltage Sector Protection” on page 37.”
2. WP#/ACC must be high when writing to upper two and lower two sectors.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appro-
priate CE# pins to V_IL. In PL129J, CE1# and CE2# are the power control and
select the lower (CE1#) or upper (CE2#) halves of the device. CE# is the power
control. OE# is the output control and gates array data to the output pins. WE#
should remain at V_IH.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
See Table 24 for timing specifications and Figure 11 for the timing diagram. I_CC1
in the DC Characteristics table represents the active current specification for
reading array data.
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
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