S71PL129JC0 Datasheet, PDF (135/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance information
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise Noted)
Read Operation
Parameter
Symbol
16M
Min.
Max.
32M
Min.
Max.
64M
Min.
Max.
Unit
Notes
Read Cycle Time
t_RC
70
1000
65
1000
65
1000
ns
1, 2
CE1# Access Time
t_CE
—
60
—
65
—
65
ns
3
OE# Access Time
t_OE
—
40
—
40
—
40
ns
3
Address Access Time
t_AA
—
60
—
65
—
65
ns
3, 5
LB# / UB# Access Time
t_BA
—
30
—
30
—
30
ns
3
Page Address Access Time
t_PAA
N/A
—
20
—
20
ns
3,6
Page Read Cycle Time
t_PRC
N/A
20
1000
20
1000
ns
1, 6, 7
Output Data Hold Time
t_OH
5
—
5
—
5
—
ns
3
CE1# Low to Output Low-Z
t_CLZ
5
—
5
—
5
—
ns
4
OE# Low to Output Low-Z
t_OLZ
0
—
0
—
0
—
ns
4
LB# / UB# Low to Output Low-Z
t_BLZ
0
—
0
—
0
—
ns
4
CE1# High to Output High-Z
t_CHZ
—
20
—
20
—
20
ns
3
OE# High to Output High-Z
t_OHZ
—
20
—
14
—
14
ns
3
LB# / UB# High to Output High-Z
t_BHZ
—
20
—
20
—
20
ns
3
Address Setup Time to CE1# Low
t_ASC
−6
—
–6
—
–6
—
ns
Address Setup Time to OE# Low
t_ASO
10
—
10
—
10
—
ns
Address Invalid Time
t_AX
—
10
—
10
—
10
ns
5, 8
Address Hold Time from CE1# High
t_CHAH
-6
—
–6
—
–6
—
ns
9
Address Hold Time from OE# High
t_OHAH
-6
—
–6
—
–6
—
ns
WE# High to OE# Low Time for Read t_WHOL
10
1000
12
—
25
—
ns
10
CE1# High Pulse Width
t_CP
10
—
12
—
12
—
ns
Notes:
1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21. If needed by system
operation, please contact local Spansion representative for the relaxation of 1µs limitation.
2. Address should not be changed within minimum t_RC.
3. The output load 50 pF with 50 ohm termination to V_DD x 0.5 (16M), The output load 50 pF (32M and 64M).
4. The output load 5pF.
5. Applicable to A3 to A21 (32M and 64M) when CE1# is kept at Low.
6. Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for the page address access.
7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 µs. In other
words, Page Read Cycle must be closed within 4 µs.
8. Applicable when at least two of address inputs among applicable are switched from previous state.
9. t_RC(min) and t_PRC(min) must be satisfied.
10. If actual value of t_WHOL is shorter than specified minimum values, the actual t_AA of following Read can become longer by the
amount of subtracting the actual value from the specified minimum value.
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
135