S71PL129JC0 Datasheet, PDF (132/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance Information
Power Down Program Sequence
The program requires 6 read/write operations with a unique address. Between
each read/write operation requires that device be in standby mode. The following
table shows the detail sequence.
Cycle #
1st
2nd
3rd
4th
5th
6th
Operation
Read
Write
Write
Write
Write
Read
Address
3FFFFFh (MSB)
3FFFFFh
3FFFFFh
3FFFFFh
3FFFFFh
Address Key
Data
Read Data (RDa)
RDa
RDa
Don’t Care (X)
X
Read Data (RDb)
The first cycle reads from the most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle.
If the second or third cycle is written into the different address, the program is
cancelled, and the data written by the second or third cycle is valid as a normal
write operation.
The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles
is “don’t care.” If the fourth or fifth cycles are written into different address, the
program is also cancelled but write data might not be written as normal write
operation.
The last cycle is to read from specific address key for mode selection.
Once this program sequence is performed from a Partial mode to the other Partial
mode, the written data stored in memory cell array can be lost. So, it should per-
form this program prior to regular read/write operation if Partial mode is used.
Address Key
The address key has following format.
Mode
32M
64M
A21
Sleep (default)
Sleep (default)
1
4M Partial
N/A
1
8M Partial
8M Partial
1
N/A
16M Partial
1
Address
A20
A19
A18 - A0
1
1
1
1
0
1
0
1
1
0
0
1
Binary
3FFFFFh
37FFFFh
2FFFFFh
27FFFFh
132
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004