S71PL129JC0 Datasheet, PDF (141/149 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory

Advance information
tRC
tAX
ADDRESS
(A21-A3)
ADDRESS
(A2-A0)
ADDRESS VALID
tRC
tPRC
ADDRESS
VALID
tAA
ADDRESS
VALID
tPAA
CE1# _Low
tASO
tOE
tRC
tAx
ADDRESS VALID
tRC
tPRC
ADDRESS
VALID
tAA
ADDRESS
VALID
tPAA
OE#
tBA
LB#/UB#
DQ
tOLZ
tOH
tOH
tBLZ
(Output)
tOH
tOH
VALID DATA OUTPUT
(Normal Access)
Notes:
1. This timing diagram assumes CE2=H and WE#=H.
2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
VALID DATA OUTPUT
(Page Access)
Figure 59. Read Timing #5 (Random and Page Address Access for 32M and 64M Only)
Write Timings
ADDRESS
CE1#
WE#
LB#, UB#
tWC
ADDRESS VALID
tAS
tCW
tWR
tAS
tWP
tWR
tAS
tBW
tWR
tOHCL
OE#
tDS
tDH
DQ
(Input)
Note: This timing diagram assumes CE2=H.
VALID DATA INPUT
Figure 60. Write Timing #1 (Basic Timing)
tAS
tCP
tAS
tWHP
tAS
tBHP
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
141