C8051F2XX Datasheet, PDF (94/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
Disable WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment
illustrates disabling the WDT.
CLR
MOV
MOV
SETB
EA
WDTCN,#0DEh
WDTCN,#0ADh
EA
; disable all interrupts
; disable watchdog timer
;
; re-enable interrupts
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is
ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes.
Disable WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored
until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications alays
intending to use the watchdog should write 0xFF to WDTCN in their initialization code.
Setting WDT Interval
WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
4^3+WDTCN[2:0] x T_SYSCLK , (where T_SYSCLK is the system clock period).
For a 2.0 MHz system clock, this provides an interval range of 32msec to 524msec. WDTCN.7 must be
written as 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] is
111b after a system reset.
SFR Definition 12.1. WDTCN: Watchdog Timer Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
xxxxx111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xFF
Bits7–0:
Bit4:
Bits2–0:
WDT Control
Writing 0xA5 both enables and reloads the WDT.
Writing 0xDE followed within 4 clocks by 0xAD disables the WDT.
Writing 0xFF locks out the disable feature.
Watchdog Status Bit (when Read)
Reading the WDTCN.[4] bit indicates the Watchdog Timer Status.
0: WDT is inactive
1: WDT is active
Watchdog Timeout Interval Bits
The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits,
WDTCN.7 must be set to 0.
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Rev. 1.6