C8051F2XX Datasheet, PDF (43/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 6.2. ADC0CF: ADC Configuration (‘F220/1/6 and ‘F206)
R/W
R/W
R/W
R/W
ADCSC2 ADCSC1 ADCSC0
-
Bit7
Bit6
Bit5
Bit4
R/W
R/W
R/W
R/W
Reset Value
-
AMPGN2 AMPGN1 AMPGN0 01100000
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xBC
Bits7–5:
Bits4–3:
Bits2–0:
ADCSC2–0: ADC SAR Conversion Clock Period Bits
000: SAR Conversion Clock = 1 System Clock
001: SAR Conversion Clock = 2 System Clocks
010: SAR Conversion Clock = 4 System Clocks
011: SAR Conversion Clock = 8 System Clocks
1xx: SAR Conversion Clock = 16 Systems Clocks
NOTE: SAR conversion clock should be less than or equal to 2MHz.
UNUSED. Read = 00b; Write = don't care
AMPGN2–0: ADC Internal Amplifier Gain
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
1x: Gain = 0.5
Rev. 1.6
43