C8051F2XX Datasheet, PDF (118/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
16.1. UART Operational Modes
The UART provides four operating modes (one synchronous and three asynchronous) selected by setting
configuration bits in the SCON register. These four modes offer different baud rates and communication
protocols. The four modes are summarized in Table 16.1 below. Detailed descriptions follow.
Mode
0
1
2
3
Synchronization
Synchronous
Asynchronous
Asynchronous
Asynchronous
Table 16.1. UART Modes
Baud Clock
SYSCLK/12
Timer 1 or Timer 2 Overflow
SYSCLK/32 or SYSCLK/64
Timer 1 or Timer 2 Overflow
Data Bits
8
8
9
9
Start/Stop Bits
None
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
16.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the
RX pin. The TX pin provides the shift clock for both transmit and receive. The MCU must be the master
since it generates the shift clock for transmission in both directions (see the interconnect diagram in
Figure 16.2).
Eight data bits are transmitted/received, LSB first (see the timing diagram in Figure 16.3). Data transmis-
sion begins when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt Flag
(SCON.1) is set at the end of the eighth bit time. Data reception begins when the REN Receive Enable bit
(SCON.4) is set to logic 1 and the RI Receive Interrupt Flag (SCON.0) is cleared. One cycle after the
eighth bit is shifted in, the RI flag is set and reception stops until software clears the RI bit. An interrupt will
occur if enabled when either TI or RI are set.
The Mode 0 baud rate is system clock frequency divided by twelve.
TX
C8051Fxxx
RX
CLK
DATA
Shift
Reg.
8 Extra Outputs
Figure 16.2. UART Mode 0 Interconnect
RX (data out)
TX (clk out)
MODE 0 TRANSMIT
D0
D1
D2
D3
D4
D5
D6
D7
RX (data in)
MODE 0 RECEIVE
D0
D1
D2
D3
D4
D5
D6
D7
TX (clk out)
Figure 16.3. UART Mode 0 Timing Diagram
118
Rev. 1.6