C8051F2XX Datasheet, PDF (139/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
18. JTAG
Description
The MCU has an on-chip JTAG interface and logic to support Flash read and write operations and non-
intrusive in-circuit debug. The C8051F2xx may be placed in a JTAG test chain in order to maintain only
one JTAG interface in a system for boundary scan of other parts, and still utilize the C8051F2xx debug and
Flash programming. However, the C8051F2xx does NOT support boundary scan and will act as BYPASS
as specified in IEEE 1149.1.
The JTAG interface is implemented via four dedicated pins on the MCU, which are TCK, TMS, TDI, and
TDO. These pins are all 5 volt tolerant.
Through the 16-bit JTAG Instruction Register (IR), five instructions shown in JTAG Register Definition 18.1
can be commanded. These commands can either select the device ID code, or select registers for Flash
programming operations. BYPASS is shown to illustrate its default setting. There are four Data Registers
associated with the Flash read and write operations on the MCU.
JTAG Register Definition 18.1. IR: JTAG Instruction
Bit15
Reset Value
0x0000
Bit0
IR value
0x0004
0xFFFF
0x0082
0x0083
0x0084
0x0085
Instruction
IDCODE
BYPASS
Flash Control
Flash Data
Flash Address
Flash Scale
Description
Selects device ID Register
Selects bypass Data Register and is DEFAULT for the device. Note:
The device does NOT support boundary scan. However, it may be
placed in a scan chain and bypassed in a system of other devices utiliz-
ing boundary scan.
Selects FLASHCON Register to control how the interface logic
responds to reads and writes to the FLASHDAT Register
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects FLASHADR Register which holds the address of all Flash read,
write, and erase operations
Selects FLASHSCL Register which controls the prescaler used to gen-
erate timing signals for Flash operations
Rev. 1.6
139