C8051F2XX Datasheet, PDF (90/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
11. On-Chip XRAM (C8051F206/226/236)
The C8051F206/226/236 features 1024 Bytes of RAM mapped into the external data memory space. All
address locations may be accessed using the external move instruction (MOVX) and the data pointer
(DPTR), or using indirect MOVX addressing mode. If the MOVX instruction is used with an 8-bit operand
(such as @R1), then the high byte is the External Memory Interface Control Register (EMI0CN, shown in
SFR Definition 11.1). Addressing using 8 bits will map to one of four 256-byte pages, and these pages are
selected by setting the PGSEL bits in the EMI0CN register.
NOTE: The MOVX instruction is also used for write to the Flash memory. Please see section 10 for
details. The MOVX instruction will access XRAM by default.
For any of the addressing modes, the upper 6 bits of the 16-bit external data memory address word are
"don't cares". As a result, the 1024-byte RAM is mapped modulo style ("wrap around") over the entire 64k
of possible address values. For example, the XRAM byte at address 0x0000 is also at address 0x0400,
0x0800, 0x0C00, 0x1000, etc. This feature is useful when doing a linear memory fill, as the address
pointer does not have to be reset when reaching the RAM block boundary.
SFR Definition 11.1. EMI0CN: External Memory Interface Control
R
R
R
R
R
R
R/W
R/W
Reset Value
-
-
-
-
-
-
PGSEL1 PGSEL0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xAF
Bits7–2: Not Used -read only 000000b
Bits1–0: XRAM Page Select Bits PGSEL[1:0]
The XRAM Page Select bits provide the high byte of the 16-bit external memory address
when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. The
upper 6 bits are "don't cares", so the 1k address blocks are repeated modulo over the entire
data memory address space.
00:0x000 – 0x0FF
01:0x100 – 0x1FF
10:0x200 – 0x2FF
11:0x300 – 0x3FF
90
Rev. 1.6