C8051F2XX Datasheet, PDF (134/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
17.2.1. Mode 0: 16-bit Counter/Timer with Capture
In this mode, Timer 2 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the
T2EX input pin causes the 16-bit value in Timer 2 (TH2, TL2) to be loaded into the capture registers
(RCAP2H, RCAP2L).
Timer 2 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the external T2 input
pin as its clock source when operating in Counter/Timer with Capture mode. Clearing the C/T2 bit
(T2CON.1) selects the system clock as the input for the timer (divided by one or twelve as specified by the
Timer Clock Select bit T2M in CKCON). When C/T2 is set to logic 1, a high-to-low transition at the T2 input
pin increments the counter/timer register. As the 16-bit counter/timer register increments and overflows
from 0xFFFF to 0x0000, the TF2 timer overflow flag (T2CON.7) is set and an interrupt will occur if the inter-
rupt is enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RL2 (T2CON.0)
and the Timer 2 Run Control bit TR2 (T2CON.2) to logic 1. The Timer 2 External Enable EXEN2
(T2CON.3) must also be set to logic 1 to enable a capture. If EXEN2 is cleared, transitions on T2EX will
be ignored.
12
0
SYSCLK
1
0
T2
PORT0
MUX
1
TR2
CKCON
TTT
210
MMM
TCLK
TL2
TH2
T2EX
EXEN2
PORT0
MUX
Capture
RCAP2L RCAP2H
Figure 17.4. T2 Mode 0 Block Diagram
CP/RL2
C/T2
TR2
EXEN2
TCLK
RCLK
EXF2
TF2
Interrupt
134
Rev. 1.6