C8051F2XX Datasheet, PDF (40/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
6. ADC (12-Bit, C8051F206 Only)
Description
The ADC subsystem for the C8051F206 consists of configurable analog multiplexer (AMUX), a program-
mable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC with integrated
track-and-hold and programmable window detector (see Figure 6.1). The AMUX, PGA, Data Conversion
Modes, and Window Detector are all configurable under software control via the Special Function Regis-
ter's shown in Figure 6.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the
ADCEN bit in the ADC Control register (ADC0CN, Figure 6.5) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0.
ADC0GTH
ADC0GTL
AIN0-31 are port 0-3
pins -- any external
port pin may be configured
as an analog input
AIN0
32-to-1
AMUX
AIN31
ADCEN
VDD
X
+
-
GND
GND
ADC0LTH
VDD
ADC0LTL
24
VDD VREF
Dig
Comp
ADWINT
12
12-Bit
SAR
12
ADC
T2 OV
ADBUSY(w)
AMX0SL
ADC0CF
ADC0CN
Figure 6.1. 12-Bit ADC Functional Block Diagram
6.1. Analog Multiplexer and PGA
Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the
desired analog input pin. (See SFR Definition 5.1). When the AMUX is enabled, the user selects which
port is to be used (bits PRTSL0–1), and then the pin in the selected port (bits PINSL0–2) to be the analog
input.
The PGA amplifies the AMUX output signal by an amount determined by the states of the AMPGN2–0 bits
in the ADC Configuration register, ADC0CF (SFR Definition 5.2). The PGA can be software-programmed
for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to a gain of 1 on reset.
40
Rev. 1.6