C8051F2XX Datasheet, PDF (69/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
Table 9.3. Special Function Registers
SFR’s are listed in alphabetical order.
Address
Register
0xE0
ACC
0xBC
ADC0CF
0xE8
ADC0CN
0xC5
ADC0GTH¹
0xC4
ADC0GTL⁴
0xBF
ADC0H¹
0xBE
ADC0L⁴
0xC7
ADC0LTH¹
0xCE
ADC0LTL⁴
0xBB
AMX0SL
0xF0
B
0x8E
CKCON
0x9E
CPT0CN
0x9F
CPT1CN
0x83
DPH
0x82
DPL
0xE6
EIE1
0xE7
EIE2
0xF6
EIP1
0xF7
EIP2
0xAF
EMI0CN³
0xB7
FLACL
0xB6
FLSCL
0xA8
IE
0xB8
IP
0xB2
OSCICN
0xB1
OSCXCN
0x80
P0
0x90
P1
0xA0
P2
0xB0
P3
0xF1
P0MODE
0xF2
P1MODE
0xF3
P2MODE
0xF4
P3MODE²
0x87
PCON
Description
Accumulator
ADC Configuration
ADC Control
ADC Greater-Than Data Word (High Byte)
ADC Greater-Than Data Word (Low Byte)
ADC Data Word (High Byte)
ADC Data Word (Low Byte)
ADC Less-Than Data Word (High Byte)
ADC Less-Than Data Word (Low Byte)
ADC MUX Channel Selection
B Register
Clock Control
Comparator 0 Control
Comparator 1 Control
Data Pointer (High Byte)
Data Pointer (Low Byte)
Extended Interrupt Enable 1
Extended Interrupt Enable 2
External Interrupt Priority 1
External Interrupt Priority 2
External Memory Interface Control
Flash Memory Read Limit
Flash Memory Timing Prescaler
Interrupt Enable
Interrupt Priority Control
Internal Oscillator Control
External Oscillator Control
Port 0 Latch
Port 1 Latch
Port 2 Latch
Port 3 Latch
Port0 Digital/Analog Output Mode
Port1 Digital/Analog Output Mode
Port2 Digital/Analog Output Mode
Port3 Digital/Analog Output Mode
Power Control
Page No.
73
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56
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71
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90
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89
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84
Rev. 1.6
69