C8051F2XX Datasheet, PDF (126/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
TR0
GATE0
0
X
1
0
1
1
1
1
X = Don’t Care
/INT0
X
X
0
1
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Setting TR0 does not reset the timer register. The timer register should be initialized to the desired value
before enabling the timer.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0.
SYSCLK
T0
12
0
1
PORT0
MUX
TR0
CKCON
TTT
210
MMM
0
1
TMOD
GCT T GCT T
A _{/ 11}A _{/ 00}
T
E
T
MM
T
E
T MM
1 110 0 010
TCLK
TL0
(5 bits)
TH0
(8 bits)
GATE0
/INT0
PORT0
MUX
Figure 17.1. T0 Mode 0 Block Diagram
TF1
TR1
TF0
Interrupt
TR0
IE1
IT1
IE0
IT0
17.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
126
Rev. 1.6