C8051F2XX Datasheet, PDF (25/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
4. Pinout and Package Definitions
Table 4.1. Pin Definitions
Name
V_DD
GND
MONEN
TCK
TMS
TDI
TDO
XTAL1
XTAL2
RST
VREF
CP0+
CP0-
CP0
CP1+
CP1-
CP1
P0.0/TX
P0.1/RX
P0.2/INT0
‘F206,
F220,
226,
230,
236
‘F221,
231
48-Pin 32-Pin
Type
Description
11,31 8
Digital Voltage Supply.
5,6,8, 9
13,32
12
Ground. (Note: Pins 5,6, and 8 on the 48-pin package are not
connected (NC), but it is recommended that they be connected to
ground.)
D In Monitor Enable (on 48 pin package ONLY). Enables reset volt-
age monitor function when pulled high (logic “1”).
25
17 D In
JTAG Test Clock with internal pull-up.
26
18 D In
JTAG Test-Mode Select with internal pull-up.
28
20 D In JTAG Test Data Input with internal pull-up. TDI is latched on a
rising edge of TCK.
27
19 D Out JTAG Test Data Output. Data is shifted out on TDO on the falling
edge of TCK. TDO output is a tri-state driver.
9
6 A In Crystal Input. This pin is the return for the internal oscillator cir-
cuit for a crystal or ceramic resonator. For a precision internal
clock, connect a crystal or ceramic resonator from XTAL1 to
XTAL2. If overdriven by an external CMOS clock, this becomes
the system clock.
10
7 A Out Crystal Output. This pin is the excitation driver for a crystal or
ceramic resonator.
14
10 D I/O Chip Reset. Open-drain output of internal Voltage Supply moni-
tor. Is driven low when V_DD is < 2.7V and MONEN=1, or when a
‘1’is written to PORSF. An external source can force a system
reset by driving this pin low.
7
5 A I/O Voltage Reference. When configured as an input, this pin is the
voltage reference for the ADC. Otherwise, V_DD will be the refer-
ence. NOTE: this pin is Not Connected (NC) on ‘F230/1/6.
4
4 A In
Comparator 0 Non-Inverting Input.
3
3 A In
2
2 D Out
1
1 A In
Comparator 0 Inverting Input.
Comparator 0 Output
Comparator 1 Non-Inverting Input.
48
32 A In
Comparator 1 Inverting Input.
47
31 D Out
Comparator 1 Output
40
28 D I/O Port0 Bit0. (See the Port I/O Sub-System section for complete
A In
description).
39
27 D I/O Port0 Bit1. (See the Port I/O Sub-System section for complete
A In
description).
38
26 D I/O Port0 Bit2. (See the Port I/O Sub-System section for complete
A In
description).
Rev. 1.6
25