C8051F2XX Datasheet, PDF (14/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
Digital Power
VDD
GND
GND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
NC
NC
NC
NC
NC
1024 Byte
JTAG
Logic
Emulation HW
8
0
XRAM
(Available in
'F236)
VDD
Monitor,
WDT
5 ^Reset
1
C
8kbyte
FLASH
256 byte
SRAM
External
Oscillator
Circuit
o SFR Bus
r System Clock
Internal
e
Oscillator
Clock & Reset
Configuration
Port I/O Mode
& Config.
Port 0
Latch
P
UART
0
Timer 0
M
U
Timer 1
X
Timer 2
Port 1
Latch
P
CP0+
1
CP0
CP0 _CP0-
M
CP1+
U
CP1
CP1 _CP1-
X
Comparator
Config.
P
Port 2
2
Latch
SPI
M
U
Port Mux
X
Control
Port 3
Latch
P
P0.0/TX
0
P0.1/RX
P0.2//INT0
P0.3//INT1
D
P0.4/T0
r
P0.5/T1
v
P0.6/T2
P0.7/T2EX
P
P1.0/CP0+
1
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
D
P1.4/CP1-
r
P1.5/CP1
v
P1.6/SYSCLK
P1.7
P
P2.0/SCK
2
P2.1/MISO
P2.2/MOSI
P2.3/NSS
D
P2.4
r
P2.5
v
P2.6
P2.7
P
P3.0
3
P3.1
P3.2
P3.3
D
P3.4
r
P3.5
v
P3.6
P3.7
Figure 1.3. C8051F230 and C8051F236 Block Diagram (48 TQFP)
14
Rev. 1.6