C8051F2XX Datasheet, PDF (68/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
9.3. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.3 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indetermi-
nate effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in
Table 9.3, for a detailed description of each register.
Table 9.2. Special Function Register Memory Map
F8 SPI0CN
WDTCN
F0
B
P0MODE P1MODE P2MODE _P3MODE²
EIP1
EIP2
E8 _ADC0CN¹
RSTSRC
E0
ACC PRT0MX PRT1MX PRT2MX
EIE1
EIE2
D8
D0
PSW REF0CN
C8 T2CON
RCAP2L RCAP2H TL2
TH2
C0
ADC0GTL⁴ ADC0GTH¹ ADC0LTL⁴ ADC0LTH¹
B8
IP
AMX0SL¹ ADC0CF¹
ADC0L⁴ ADC0H¹
B0
P3
OSCXCN OSCICN
FLSCL FLACL
A8
IE
SWCINT
EMI0CN³
A0
P2
PRT0CF PRT1CF PRT2CF PRT3CF
98
SCON
SBUF SPI0CFG SPI0DAT
SPI0CKR CPT0CN CPT1CN
90
P1
88 TCON TMOD
TL0
TL1
TH0
TH1
CKCON PSCTL
80
P0
SP
DPL
DPH
PCON
0(8)
Bit Addressable
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
Notes:
1. C8051F230/1/6 Do not have these registers.
2. C8051F221/231 Does not have this register (32 pin package).
3. On the C8051F206 and C8051F226/236 only.
4. On the C8051F206 only (12-bit ADC)
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Rev. 1.6