C8051F2XX Datasheet, PDF (21/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
ADC data is continuously monitored by a programmable window detector, which interrupts the CPU when
data is within the user-programmed window. This allows the ADC to monitor key system voltages in back-
ground mode, without the use of CPU resources.
AIN0
AIN1
AIN0-31 are port 0-3
pins -- any external
port pin may be configured as
an analog input
(only 22 input port pins on
'F221)
AIN31
32-to-1
AMUX
Programmable
Gain Amp
X
+
-
GND
VREF
VDD
100ksps
SAR
ADC
Control & Data
SFR's
SFR Bus
Figure 1.10. ADC Diagram
1.7. Comparators
The MCU's have two on-chip voltage comparators. The inputs of the comparators are available at pack-
age pins as illustrated in Figure 1.11. Each comparator's hysteresis is software programmable via special
function registers (SFR's). Both voltage level and positive/negative going symmetry can be easily pro-
grammed by the user. Additionally, comparator interrupts can be implemented on either rising or falling-
edge output transitions. Please see 8.‘Comparators” on page 52 for details.
Rev. 1.6
21