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C8051F2XX Datasheet, PDF (142/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family
C8051F2xx
JTAG Register Definition 18.4. FLASHDAT: JTAG Flash Data
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
FAIL
Bit1
BUSY
Bit0
Reset Value
0000000000
This register is used to read or write data to the Flash memory across the JTAG interface.
Bits9–2:
Bit1:
Bit0:
DATA7–0: Flash Data Byte.
FAIL: Flash Fail Bit.
0:
Previous Flash memory operation was successful.
1:
Previous Flash memory operation failed. Usually indicates the associated memory
location was locked.
BUSY: Flash Busy Bit.
0:
Flash interface logic is not busy.
1:
Flash interface logic is processing a request. Reads or writes while BUSY = 1 will
not initiate another operation
JTAG Register Definition 18.5. FLASHSCL: JTAG Flash Scale
FOSE FRAE
-
Bit7
Bit6
Bit5
Reset Value
-
FLSCL3 FLSCL2 FLSCL1 FLSCL0 00000000
Bit4
Bit3
Bit2
Bit1
Bit0
This register controls the Flash read timing circuit and the prescaler required to generate the correct
timing for Flash operations.
Bit7:
FOSE: Flash One-Shot Enable Bit.
0: Flash read strobe is a full clock-cycle wide.
1: Flash read strobe is 50nsec.
Bit6:
FRAE: Flash Read Always Bit.
0: The Flash output enable and sense amplifier enable are on only when needed to read the
Flash memory.
1: The Flash output enable and sense amplifier enable are always on. This can be used to
limit the variations in digital supply current due to switching the sense amplifiers, thereby
reducing digitally induced noise.
Bits5–4: UNUSED. Read = 00b, Write = don't care.
Bits3–0:
FLSCL3–0: Flash Prescaler Control Bits.
The FLSCL3–0 bits control the prescaler used to generate timing signals for Flash opera-
tions. Its value should be written before any Flash write or erase operations are initiated.
The value written should be the smallest integer for which:
FLSCL[3:0] > log2(fSYSCLK / 50kHz)
Where fSYSCLK is the system clock frequency. All Flash read/write/erase operations are
disallowed when FLSCL[3:0] = 1111b.
142
Rev. 1.6