C8051F2XX Datasheet, PDF (107/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 14.9. P1MODE: Port1 Digital/Analog Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xF2
Bits7–0: Port1 Digital/Analog Output Mode
0: Corresponding Port1 pin Digital Input disabled. (For analog use, i.e., ADC or
comparators).
1: Corresponding Port1 pin Digital Input is enabled.
SFR Definition 14.10. P2: Port2 Register
R/W
P2.7
Bit7
R/W
P2.6
Bit6
R/W
P2.5
Bit
R/W
P2.4
Bit4
R/W
P2.3
Bit3
R/W
P2.2
Bit2
R/W
P2.1
Bit1
R/W
Reset Value
P2.0
11111111
Bit0
SFR Address:
(bit addressable) 0xA0
Bits7–0:
P2.[7:0]
(Write - Output appears on I/O pins per PRT0MX, PRT1MX, and PRT2MX registers)
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding PRT2CF.n bit = 0)
(Read - Regardless of PRT0MX, PRT1MX, and PRT2MX Register settings).
0: P2.n is logic low.
1: P2.n is logic high.
SFR Definition 14.11. PRT2CF: Port2 Configuration Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–0: PRT2CF.[7:0]: Output Configuration Bits for P2.7–P2.0 (respectively)
0: Corresponding P2.n Output Mode is Open-Drain.
1: Corresponding P2.n Output Mode is Push-Pull.
Reset Value
00000000
SFR Address:
0xA6
Rev. 1.6
107