C8051F2XX Datasheet, PDF (104/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 14.2. PRT1MX: Port I/O MUX Register 1
R
R/W
R
R
R
R
R/W
R/W
Reset Value
-
SYSCKE
-
-
-
-
CP1OEN CP0OEN 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xE2
Bit7: UNUSED. Read = 0.
Bit6: SYSCKE: SYSCLK Output Enable Bit
0: SYSCLK unavailable at the port pin.
1: SYSCLK output routed to pin P1.6
Bits 5–2: UNUSED. Read = 0000b, Write = don't care.
Bit1: CP1OEN: Comparator 1 Output Enable bit.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port Pin P1.5.
Bit0: CP0OEN: Comparator 0 Output Enable Bit
0: CP0 unavailable at port pin.
1: CP0 routed to port pin P1.2.
SFR Definition 14.3. PRT2MX: Port I/O MUX Register 2
R/W
R/W
R/W
R/W
R/W
R/W
GWPUD P3WPUD P2WPUD P1WPUD P0WPUD
-
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
R/W
Reset Value
-
SPI0OEN 00000000
Bit1
Bit0 SFR Address:
0xE3
Bit 7: GWPUD: Global Port I/O Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for all ports.
1: Weak Pull-ups Disabled (Bits 6–3 Don't cares)
Bit 6: P3WPUD: Port 3 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 3
1: Weak Pull-ups Disabled for port 3
Bit 5: P2WPUD: Port 2 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 2.
1: Weak Pull-ups Disabled for port 2
Bit 4: P1WPUD: Port 1 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 1
1: Weak Pull-ups Disabled for port 1
Bit 3: P0WPUD: Port 0 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 0
1: Weak Pull-ups Disabled for port 0
Bits 2–1: UNUSED. Read = 00b, Write = don't care.
Bit 0: SPI0OEN: SPI Bus I/O Enable Bit.
0: SPI I/O unavailable at port pins.
1: SCK, MISO, MOSI, NSS routed to pins P2.0, P2.1, P2.2, and P2.3 respectively.
104
Rev. 1.6