C8051F2XX Datasheet, PDF (62/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
Table 9.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
MOV A,#data
MOV Rn,A
MOV Rn,direct
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct,direct
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
MOV @Ri,#data
MOV DPTR,#data16
MOVC A,@A+DPTR
MOVC A,@A+PC
MOVX A,@Ri
MOVX @Ri,A
MOVX A,@DPTR
MOVX @DPTR,A
PUSH direct
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Boolean Manipulation
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
JC rel
Description
Move immediate to A
Move A to register
Move direct byte to register
Move immediate to register
Move A to direct byte
Move register to direct byte
Move direct byte to direct
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load data pointer with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
Clear carry
Clear direct bit
Set carry
Set direct bit
Complement carry
Complement direct bit
AND direct bit to carry
AND complement of direct bit to carry
OR direct bit to carry
OR complement of direct bit to carry
Move direct bit to carry
Move carry to direct bit
Jump if carry is set
Bytes
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
1
2
1
2
2
2
2
2
2
2
2
Clock
Cycles
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
1
2
1
2
1
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2
2
2
2
2
2
2/3
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Rev. 1.6