C8051F2XX Datasheet, PDF (75/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 9.7. SWCINT: Software Controlled Interrupt Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
SCI3
SCI2
SCI1
SCI0
-
-
-
-
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xAD
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–0:
SCI3: Software Controlled Interrupt 3 Bit.
If enabled, writing a logic 1 to this interrupt control bit will cause the CPU to vector to the
SCI3 interrupt service routine. This bit is not cleared in hardware. It must be cleared by
software.
SCI2: Software Controlled Interrupt 2 Bit.
If enabled, writing a logic 1 to this interrupt control bit will cause the CPU to vector to the
SCI2 interrupt service routine. This bit is not cleared in hardware. It must be cleared by
software.
SCI1: Software Controlled Interrupt 1 Bit.
If enabled, writing a logic 1 to this interrupt control bit will cause the CPU to vector to the
SCI1 interrupt service routine. This bit is not cleared in hardware. It must be cleared by
software.
SCI0: Software Controlled Interrupt 0 Bit.
If enabled, writing a logic 1 to this interrupt control bit will cause the CPU to vector to the
SCI0 interrupt service routine. This bit is not cleared in hardware. It must be cleared by
software.
UNUSED. Read = 0000b, Write = don't care.
Interrupt Source
Reset
External Interrupt 0 (/INT0)
Timer 0 Overflow
External Interrupt 1 (/INT1)
Timer 1 Overflow
Serial Port (UART)
Timer 2 Overflow (or EXF2)
Serial Peripheral Interface
ADC0 Window Comparison
Comparator 0 Falling Edge
Comparator 0 Rising Edge
Comparator 1 Falling Edge
Comparator 1 Rising Edge
Table 9.4. Interrupt Summary
Interrupt
Vector
0x0000
0x0003
0x000B
0x0013
0x001B
0x0023
0x002B
0x0033
0x0043
0x0053
0x005B
0x0063
0x006B
Priority
Order
Top
0
1
2
3
4
5
6
8
10
11
12
13
Interrupt-Pending Flag
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI (SCON.0)
TI (SCON.1)
TF2 (T2CON.7)
SPIF (SPI0STA.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
ADWINT (ADC0CN.2)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
Enable
Always enabled
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES (IE.4)
ET2 (IE.5)
ESPI0 (EIE1.0)
EWADC0 (EIE1.2)
ECP0F (EIE1.4)
ECP0R (EIE1.5)
ECP1F (EIE1.6)
ECP1R (EIE1.7)
Rev. 1.6
75