C8051F2XX Datasheet, PDF (102/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
T0,T1,T2
Timers
UART
External
INT0 & INT1
Comparators
0&1
SYSCLK
SPI
PRTnMX
Registers
Port
0
MUX
PRTnCF &
PnMODE
registers
Port0 I/O Cell
Port
1
MUX
Port1 I/O Cell
Port
2
MUX
Port2 I/O Cell
External
pins
P0.0/TX
P0.1/RX
P0.2/INT0
P0.3/INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
Any port pin may be
configured via software as an
analog input to the ADC
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P2.6
P2.7
ADC
P3.0
P3.1
P3.2
A
M
U
X
Port3 I/O Cell
P3.3
P3.4
P3.5
P3.6
P3.7
Figure 14.1. Port I/O Functional Block Diagram
To Comparator Input (on
port 1 only)
ADC
Analog Select
WEAK PUD
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
VDD
VDD
(WEAK)
PORT
PAD
Digital Input
DGND
Digital Enable
Figure 14.2. Port I/O Cell Block Diagram
102
Rev. 1.6