C8051F2XX Datasheet, PDF (106/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 14.6. P0MODE: Port0 Digital/Analog Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xF1
Bits7–0: Port0 Digital/Analog Input Mode
0: Corresponding Port0 pin Digital Input disabled. (For analog use, i.e., ADC).
1: Corresponding Port0 pin Digital Input is enabled.
SFR Definition 14.7. P1: Port1 Register
R/W
P1.7
Bit7
R/W
P1.6
Bit6
R/W
P1.5
Bit5
R/W
P1.4
Bit4
R/W
P1.3
Bit3
R/W
P1.2
Bit2
R/W
P1.1
Bit1
R/W
Reset Value
P1.0
11111111
Bit0
SFR Address:
(bit addressable) 0x90
Bits7–0:
P1.[7:0]
(Write - Output appears on I/O pins per PRT0MX, PRT1MX, and PRT2MX registers)
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding PRT1CF.n bit = 0)
(Read - Regardless of PRT0MX, PRT1MX, and PRT2MX Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
SFR Definition 14.8. PRT1CF: Port1 Configuration Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA5
Bits7–0: PRT1CF.[7:0]: Output Configuration Bits for P1.7–P1.0 (respectively)
0: Corresponding P1.n Output Mode is Open-Drain.
1: Corresponding P1.n Output Mode is Push-Pull.
106
Rev. 1.6