C8051F2XX Datasheet, PDF (131/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 17.3. CKCON: Clock Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
T2M
T1M
T0M
-
-
-
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x8E
Bits7–6: UNUSED. Read = 00b, Write = don't care.
Bit5:
T2M: Timer 2 Clock Select.
This bit controls the division of the system clock supplied to Timer 2. This bit is ignored
when the timer is in baud rate generator mode or counter mode (i.e. C/T2 = 1).
0: Timer 2 uses the system clock divided by 12.
1: Timer 2 uses the system clock.
Bit4:
T1M: Timer 1 Clock Select.
This bit controls the division of the system clock supplied to Timer 1.
0: Timer 1 uses the system clock divided by 12.
1: Timer 1 uses the system clock.
Bit3:
T0M: Timer 0 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 0.
0: Counter/Timer uses the system clock divided by 12.
1: Counter/Timer uses the system clock.
Bits2–0: UNUSED. Read = 000b, Write = don't care.
Rev. 1.6
131