C8051F2XX Datasheet, PDF (110/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
15. Serial Peripheral Interface Bus
The Serial Peripheral Interface (SPI) provides access to a four-wire, full-duplex, serial bus. SPI supports
the connection of multiple slave devices to a master device on the same bus. A separate slave-select sig-
nal (NSS) is used to select a slave device and enable a data transfer between the master and the selected
slave. Multiple masters on the same bus are also supported. Collision detection is provided when two or
more masters attempt a data transfer at the same time. The SPI can operate as either a master or a slave.
When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system
clock frequency.
When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation
is 1/10 the system clock frequency, provided that the master issues SCK, NSS, and the serial input data
synchronously with the system clock. If the master issues SCK, NSS, and the serial input data asynchro-
nously, the maximum data transfer rate (bits/sec) must be less that 1/10 the system clock frequency. In the
special case where the master only wants to transmit data to the slave and does not need to receive data
from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate
(bits/sec) of ¼ the system clock frequency. This is provided that the master issues SCK, NSS, and the
serial input data synchronously with the system clock.
SFR Bus
SPI0CKR
SSSSSSSS
CCCCCCCC
RRRRRRRR
76543210
SPI0CFG
CCBBBF FF
K KCCCRRR
PP2 1 0SSS
HO
210
AL
SPI0CN
SWMR T S M S
PCOXX L SP
I ODOBV T I
F LFVSSEE
RY E NN
NL
SYSCLK
Clock Divide
Logic
Bit Count
Logic
SPI CONTROL LOGIC
Data Path
Control
SPI Clock
(Master Mode)
Pin Control
Interface
SPI IRQ
SCK
P
O
Tx Data
MISO _R
Pin
T
SPI0DAT
Control
2
Shift Register
76543210
Logic
Rx Data
MOSI
M
U
Receive Data Register
X
NSS
Write to
SPI0DAT
Read
SPI0DAT
P2.0 SCK
P2.1 MISO
P2.2 MOSI
P2.3 NSS
SFR Bus
Figure 15.1. SPI Block Diagram
110
Rev. 1.6