C8051F2XX Datasheet, PDF (114/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
SFR Definition 15.1. SPI0CFG: SPI Configuration
R/W
CKPHA
Bit7
R/W
CKPOL
Bit6
R
BC2
Bit5
R
BC1
Bit4
R
BC0
Bit3
R/W
SPIFRS2
Bit2
R/W
SPIFRS1
Bit1
R/W
Reset Value
SPIFRS0 00000111
Bit0 SFR Address:
0x9A
Bit7:
CKPHA: SPI Clock Phase.
This bit controls the SPI clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
Bit6:
CKPOL: SPI Clock Polarity.
This bit controls the SPI clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Bits5–3: BC2–BC0: SPI Bit Count.
Indicates which of the up to 8 bits of the SPI word have been transmitted.
BC2–BC0
Bit Transmitted
0
0
0
Bit 0 (LSB)
0
0
1
Bit 1
0
1
0
Bit 2
0
1
1
Bit 3
1
0
0
Bit 4
1
0
1
Bit 5
1
1
0
Bit 6
1
1
1
Bit 7 (MSB)
Bits2–0: SPIFRS2–SPIFRS0: SPI Frame Size.
These three bits determine the number of bits to shift in/out of the SPI shift register during a
data transfer in master mode. They are ignored in slave mode.
SPIFRS
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Bits Shifted
1
2
3
4
5
6
7
8
114
Rev. 1.6