C8051F2XX Datasheet, PDF (105/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

C8051F2xx
14.2. General Purpose Port I/O
Each I/O port is accessed through a corresponding special function register (SFR) that is both byte addres-
sable and bit addressable. When writing to a port, the value written to the SFR is latched to maintain the
output data value at each pin. When reading, the logic levels of the port’s input pins are returned regard-
less of the PRTnMX settings (i.e., even when the pin is assigned to another signal by the MUX, the Port
Register can always still read its corresponding Port I/O pin), provided its pin is configured for digital input
mode. The exception to this is the execution of the read-modify-write instructions. The read-modify-write
instructions when operating on a port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a port SFR. For these instructions, the
value of the register (not the pin) is read, modified, and written back to the SFR.
SFR Definition 14.4. P0: Port0 Register
R/W
P0.7
Bit7
R/W
P0.6
Bit6
R/W
P0.5
Bit5
R/W
P0.4
Bit4
R/W
P0.3
Bit3
R/W
P0.2
Bit2
R/W
P0.1
Bit1
R/W
Reset Value
P0.0
11111111
Bit0
SFR Address:
(bit addressable) 0x80
Bits7–0:
P0.[7:0]
(Write - Output appears on I/O pins per PRT0MX, PRT1MX, and PRT2MX Registers)
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding PRT0CF.n bit = 0)
(Read - Regardless of PRT0MX, PRT1MX, and PRT2MX Register settings).
0: P0.n pin is logic low.
1: P0.n pin is logic high.
SFR Definition 14.5. PRT0CF: Port0 Configuration Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA4
Bits7–0: PRT0CF.[7:0]: Output Configuration Bits for P0.7–P0.0 (respectively)
0: Corresponding P0.n Output mode is Open-Drain.
1: Corresponding P0.n Output mode is Push-Pull.
Rev. 1.6
105