C8051F2XX Datasheet, PDF (15/146 Pages) Silicon Laboratories – Mixed Signal 8 kB ISP Flash MCU Family

Digital Power
VDD
GND
TCK
TMS
TDI
TDO
/RST
XTAL1
XTAL2
NC
JTAG
Logic
Emulation HW
8
8kbyte
0
FLASH
5 ^Reset
VDD
Monitor,
WDT
1
256 byte
SRAM
C
External
Oscillator
Circuit
o SFR Bus
r System Clock
Internal
e
Oscillator
Clock & Reset
Configuration
C8051F2xx
Port I/O Mode
& Config.
Port 0
Latch
P
UART
0
Timer 0
M
U
Timer 1
X
Timer 2
Port 1
Latch
P
CP0+
1
CP0
CP0 _CP0-
M
CP1+
U
CP1
CP1 _CP1-
X
Comparator
Config.
P
Port 2
2
Latch
M
SPI
U
Port Mux
X
Control
Port 3
Latch
P
P0.0/TX
0
P0.1/RX
P0.2//INT0
P0.3//INT1
D
P0.4/T0
r
P0.5/T1
v
P0.6/T2
P0.7/T2EX
P
P1.0/CP0+
1
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
D
P1.4/CP1-
r
P1.5/CP1
v
P1.6/SYSCLK
P1.7
P
P2.0/SCK
2
P2.1/MISO
P2.2/MOSI
P2.3/NSS
D
P2.4
r
P2.5
v
Figure 1.4. C8051F231 Block Diagram (32 LQFP)
1.1. CIP-51^TM Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F206, C8051F220/1/6 and C8051F230/1/6 utilize Silcon Labs’ proprietary CIP-51 microcontrol-
ler core. The CIP-51 is fully compatible with the MCS-51^TM instruction set. Standard 803x/805x assem-
blers and compilers can be used to develop software. The core contains the peripherals included with a
standard 8052, including three 16-bit counter/timers, a full-duplex UART, 256 bytes of internal RAM, an
optional 1024 bytes of XRAM, 128 byte Special Function Register (SFR) address space, and four byte-
wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes
70% of its instructions in one or two system clock cycles, with only four instructions taking more than four
system clock cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to
execute them is as follows:
Instructions
26
50
5
14
7
3
1
2
1
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Rev. 1.6
15